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LH5P860
FEATURES * 65,536 x 8 bit organization * Access time: 80 ns (MAX.) * Cycle time: 140 ns (MIN.) * Single +5 V power supply * Pin compatible with 1M standard SRAM * Power consumption (MAX.): Operating: 440 mW Self refresh (TTL level): 5.5 mW Self refresh (CMOS level): 2.75 mW * TTL compatible I/O * 512 refresh cycles/8 ms (MAX.) * Available for auto-refresh and self-refresh modes * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP
CMOS 512K (64K x 8) Pseudo-Static RAM
DESCRIPTION
The LH5P860 is a 512K-bit Pseudo-Static RAM organized as 65,536 x 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock.
PIN CONNECTIONS
32-PIN DIP 32-PIN SOP RFSH NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 R/W A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
5P860-1
TOP VIEW
Figure 1. Pin Connections for DIP and SOP Packages
1
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 6 5 27 26 ROW ADDRESS A0 - A8 BUFFER SENSE AMPS I/O SELECTOR DATA IN BUFFER 13 I/O0 14 15 17 18 I/O1 I/O2 I/O3 I/O4 A9 - A15 COLUMN ADDRESS BUFFER
VBB GENERATOR
COLUMN DECODER
A10 23 A11 25 A12 4 A13 28 A14 3 A15 31
REFRESH ADDRESS COUNTER
EXT/INT ADDRESS MUX
ROW DECODER
MEMORY ARRAY 512 K
19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7
CE1 22 CE2 30
CLOCK GENERATOR
REFRESH CONTROLLER RFSH 1 OE 24 R/W 29
REFRESH TIMER
5P860-2
Figure 2. LH5P860 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A15 R/W OE RFSH CE1, CE2
Address input Read/Write input Output Enable input Refresh input Chip Enable input
I/O0 - I/O7 VCC GND NC
Data input/output Power Supply Ground No Connection
2
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Applied voltage on all pins Output short circuit current Power dissipation Operating temperature Storage temperature
VT IO PD Topr Tstg
-1.0 to +7.0 50 600 0 to +70 -65 to +150
V mA mW C C
1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC GND VIH VIL
4.5 0 2.4 -1.0
5.0 0
5.5 0 VCC + 0.3 0.8
V V V V
CAPACITANCE (TA = 0 to +70C, f = 1 MHz, VCC = 5.0 V 10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A0 - A15 Input capacitance Input/Output capacitance R/W, OE, RFSH CE1, CE 2 I/O0 - I/O7
CIN1 CIN2 CIN3 COUT1
8 5 5 10
pF pF pF pF
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Average supply current in normal operation Supply current in standby mode Average supply current in self refresh cycle Input leakage current I/O leakage current Output HIGH voltage Output LOW voltage
ICC1 ICC2 ICC3 ILI ILO VOH VOL TTL input CMOS input TTL input CMOS input 0 V V IN 6.5 V, 0 V except on test pins 0 V V OUT V CC + 0.3 V, Outputs in high-impedance state IOUT = -1.0 mA IOUT = 4.0 mA -10 -10 2.4
80 1.0 0.5 1.0 0.5 10 10
mA mA mA A A V
1, 2 1, 3 1, 4 1, 5 1, 6
0.4
V
NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time. 3. CE1 = VIH, RFSH = VIH. 4. CE1 = VCC - 0.2 V, RFSH = VCC - 0.2 V. 5. CE1 = VIH, RFSH = VIL. 6. CE1 = VCC - 0.2 V, RFSH = 0.2 V.
3
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
AC CHARACTERISTICS 1, 2, 3 (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time Output enable time from CE Output enable time from OE Output enable time from R/W Output disable time from CE Output disable time from OE Output diable time from R/W OE setup time OE hold time Write command pulse width Write command setup time Write command hold time Data setup time from R/W Data setup time from CE Data hold time from R/W Data hold time from CE Transition time (rise and fall) Refresh time interval Refresh command hold time Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh)
NOTES: 1. In order to initialize the circuit, an initialize pause of 100 s with CE1 = VIH, RFSH = VIH (or CE2 = VIL, RFSH = VIH) is required after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right): 4. Address is latched at the negative edge of CE1 or at the positive edge of CE2. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data is latched at the positive edge of R/W, at the positive edge of CE1, or at the negative edge of CE2.
tRC tRMW tCE tP tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tWP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tRHC tFC tRFD tFAP tFP tFAS tFRS
140 205 80 50 0 20 0 0 80 30 20 0 0 25 25 25 10 10 30 30 50 30 30 0 0 3 15 130 50 30 30 8,000 160 8,000 35 8 10,000
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 6 6 6 6 5 5 4 4
INPUT
2.4 V 0.8 V
2.6 V 0.6 V 2.2 V 0.8 V
OUTPUT
5P860-12
Figure 3. AC Characteristics
4
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
tRC tP VIH CE1 VIL VIH CE2 V IL tAS VIH A0 - A15 V IL VIH OE V IL tRCS VIH R/W V IL tOEA tCEA tOLZ tCLZ VOH I/O0 - I/O7 V OL tFP tFRS VIH RFSH VIL tRHC tRFD tOHZ tCHZ tRCH tAH tCE
ADDRESS INPUT
VALID-DATA OUTPUT
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P860-3
Figure 4. Read Cycle
5
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
tRC tP VIH VIL VIH VIL tAS VIH VIL tOES VIH OE V IL tWCS tWCH tWP VIH R/W V IL tDSW tDSC VOH I/O0 - I/O7 VOL tFP tFRS VIH RFSH VIL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). tRHC tRFD tDHW tDHC tAH tCE
CE1
CE2
A0 - A15
ADDRESS INPUT tOEH
DATA INPUT
5P860-4
Figure 5. Write Cycle 1 (OE = Fix `H')
6
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
tRC tP VIH CE1 VIL VIH CE2 VIL tAS VIH A0 - A15 V IL VIH VIL tWCS tWCH tWP VIH VIL tDSW tDSC VIH DIN V IL tCLZ I/O0 - I/O7 tOHZ VOH DOUT V OL tFP tFRS VIH RFSH VIL tRHC tRFD tWHZ tDHW tDHC tAH tCE
ADDRESS INPUT
OE
R/W
DATA INPUT tOLZ tWLZ tCHZ
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P860-5
Figure 6. Write Cycle 2 (OE Clock)
7
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
tRC tP VIH CE1 VIL V CE2 VIH IL tAS VIH VIL VIH VIL tWCS tWCH tWP VIH R/W V IL tDSW tDSC VIH VIL tCLZ V DOUT VOH OL tFP tFRS V RFSH VIH IL tRHC tFD tRFD tWHZ tDHW tDHC tAH tCE
A0 - A15
ADDRESS INPUT
OE
DIN I/O0 - I/O7
DATA INPUT tWLZ tCHZ
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P860-6
Figure 7. Write Cycle 3 (OE = Fix `L')
8
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
tRMW tP VIH VIL VIH VIL tAS VIH VIL tAH
CE1
CE2
A0 - A15
ADDRESS INPUT
V OE VIH IL tWCS tRCS VIH VIL tOEA tCEA tDSW tDSC tDHC VIH DIN V IL tWHZ I/O0 - I/O7 tCLZ V DOUT VOH OL tFP tFRS VIH VIL tRHC tRFD tOLZ tOHZ tWLZ tCHZ DATA INPUT tDHW tWP
R/W
DATA OUTPUT
RFSH
NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P860-7
Figure 8. Read-Modify-Write Cycle
9
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
tRC tP VIH CE1 VIL VIH CE2 V IL tAS VIH A0 - A8 VIL tOES VIH OE VIL tRCS VIH R/W V IL tRCH tAH tCE
ADDRESS INPUT tOEH
V I/O0 - I/O7 VOH OL tFP tFRS VIH RFSH VIL tRHC
OPEN
tRFD
NOTES: 1. Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). 2. A9 - A16 = Don't Care.
5P860-8
Figure 9. CE Only Refresh Cycle
10
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
V CE1 VIH IL
V CE2 VIH IL OR CE1 VIH VIL tFC V CE2 VIH IL tRFD tFP VIH VIL VOH VOL tFAP tFP tFAP tFP tRHC tFC
RFSH
I/O0 - I/O7
OPEN
NOTE: OE, R/W, A0 - A16 = Don't care
5P860-9
Figure 11. Auto Refresh Cycle
CE1
VIH VIL
V CE2 VIH IL OR V CE1 VIH IL VIH VIL tRFD tFP VIH VIL tFAS tFRS tRHC
CE2
RFSH
I/O0 - I/O7
VOH VOL
OPEN
NOTE: OE, R/W, A0 - A16 = Don't care
5P860-10
Figure 10. Self Refresh Cycle
11
LH5P860
CMOS 512K (64K x 8) Pseudo-Static RAM
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32 17
DETAIL
13.45 [0.530] 12.95 [0.510]
1 41.30 [1.626] 40.70 [1.602]
16 0.30 [0.012] 0.20 [0.008]
0 TO 15
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
12
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P860
ORDERING INFORMATION
LH5P860 Device Type X Package - ## Speed 80 Access Time (ns) D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) CMOS 512K (64K x 8) Pseudo-Static RAM Example: LH5P860N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP)
5P860-11
13

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